The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to an interconnect structure including an enhanced diffusion barrier in which a metal nitride liner component of the diffusion barrier is formed in-situ. The present disclosure also provides methods of forming such an interconnect structure.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, -based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) can be achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in an interconnect dielectric material having a dielectric constant of less than 4.0.
In a typical interconnect structure, a first diffusion barrier composed of TaN and a second diffusion barrier composed of Ta are sequentially deposited utilizing physical vapor deposition (PVD) within an opening that is formed into the interconnect dielectric material. The utilizing of two deposition steps in forming the TaN/Ta diffusion barrier adds costs and additional complexity in fabricating interconnect structures.